1. Field of the Invention
The present invention relates to a synchronous semiconductor memory and, more particularly, to a synchronous dynamic random access memory (SDRAM) having a fast (high speed) random row access function, such as a single data rate type fast cycle random access memory (SDR-FCRAM) or a double data rate type fast cycle random access memory (DDR-FCRAM) having a data rate twice that of the SDR-FCRAM.
2. Description of the Related Art
The SDRAM can realize fast random row access close to that of a static random access memory (SRAM). Hence, this SDRAM is recently extensively used as a memory having both large memory capacity and fast random row access, as the characteristic features of a DRAM.
This fast random row access of the SDRAM is accomplished by performing a random access operation (data read operation or data write operation) in synchronism with an external clock (fast clock) having a high frequency, thereby improving the data band width (=the number of data bytes per unit time).
The SDRAM has been put into practical use since the memory capacity was 4 or 16 Mbits, and most DRAMs having a memory capacity of 64 Mbits are SDRAMs. Recently, a DDR-SDRAM (double data rate type SDRAM) having a data rate twice that of the SDRAM (single data rate type SDRAM) is put into practical use to further increase the speed of the fast random row access of the DRAM.
As described above, the characteristic feature of the SDRAM is to increase the data rate, i.e., improve the data band width, by reducing the substantial access time and cycle time. However, this feature is limited when random access is performed for an internal memory cell array of a memory core, i.e., when the row address changes.
More specifically, when the row address changes, operations unique to the DRAM such as precharge performed prior to data read and data restore caused by so-called data destructive read must be performed whenever the row address changes. The time required for such an operation is called core latency, and this core latency suppresses improvements of cycle time (=random cycle time) tRC when the row address changes.
A technique for solving this problem is proposed in, e.g., reference 1: “a 20 ns Random Access Pipelined Operating DRAM” (VLSI Symp. 1998). This reference 1 disclosed a Fast Cycle RAM (to be referred to as an FCRAM hereinafter) in which random access and precharge for a memory cell array in a memory core are pipelined, in order to improve the random cycle time tRC when the row address changes.
The basic system of this FCRAM is proposed in, e.g., reference 2: International Patent Application (International Publication No.) WO98/56004 declaring priority based on Japanese Patent Application Nos. 9-145406, 9-215047, and 9-332739. This reference 2 discloses the basic system of the FCRAM, which improves the random cycle time tRC by using a pipeline operation when accessing different rows.
The FCRAM using this pipeline operation is expected to be applied to the field of networks required to transfer huge amounts of random data at high speed. In particular, SRAMs (Static RAMs) conventionally constructing a LAN switch/router system as the gate of a WAN (Wide Area Network) are recently beginning to be replaced with FCRAMs having high memory capacity and capable of fast random row access.